To overcome some of the deficiencies incurred by testing of circuit boards using conventional probing techniques, a testing technique known as boundary scan has been developed. Testing of a circuit board using the technique of boundary scan requires that each individual active device (i.e., an integrated circuit) on a circuit board be provided with a plurality of boundary-scan cells (single-bit shift registers) each connected to a separate input/output pin of the device. The boundary-scan cells in each device are coupled in a serial chain to form a boundary data register which is serially coupled with the boundary-scan register of the other devices to form a board level serial boundary-scan chain.
Testing of the devices coupled in such a serial boundary-scan chain is accomplished by shifting a stream of test bits into the chain of devices through a Test Access Port (TAP) on each device so that each bit in the stream, for interconnect test, is input to a corresponding one of the boundary-scan cells. The test bit input to each cell is then applied to the cell to update it, i.e., to replace the current value of the bit stored therein with the value of the test bit. As the bit within each boundary-scan cell associated with a device output pin is updated, the boundary-scan cells associated with each device input pin connected to this output pin will be further updated. By shifting out the bits from the boundary-scan chain after the boundary-scan registers have been updated, and by comparing the stream of bits shifted out to that expected for a chain of devices that is defect-free, a fault in any of the devices can be uncovered.
In the course of carrying out boundary-scan testing, there are circumstances when it is useful to load a test data register in a particular device in the chain with data via the boundary-scan Test Access Port (TAP). For example, a device, such as a microprocessor, might have its control store loaded with new micro-instructions, which, when executed, would cause the device to test itself. Presently, to load a plurality of L-bit segments into a test data register, successive blocks of data of the form (L.sub.1 +L+L.sub.2) bits must be shifted through the scan chain, where L.sub.1 and L.sub.2 are the cumulative numbers of scan cells in the chain upstream and downstream, respectively, of the test data register in the device to be loaded with data. The L.sub.1 and L.sub.2 bit strings preceding and succeeding, respectively, each L-bit segment of interest are chosen to be "don't care" values. To load the test data register with N separate L-bit segments, N data blocks or packets, each of the form (L.sub.1 +L+L.sub.2) bits, must be shifted through the boundary-scan chain.
The above-described data transfer scheme is very inefficient because every time a new L-bit segment is to be loaded into the test data register of a particular device, a stream of (L.sub.1 +L+L.sub.2) bits must be shifted through the entire chain, requiring at least (L.sub.1 +L+L.sub.2) clock cycles. Further, to load a large stream of L-bit segments at the device operating speed would require a very high transfer rate which may not be obtainable.
Thus, there is a need for an efficient technique for transferring data to and from a device in a scan chain.